Embodiments of the inventive concept relate generally to semiconductor devices and latency circuits for the semiconductor devices. More particularly, embodiments of the inventive concept relate to semiconductor devices and latency circuits adapted to provide stable latency in spite of frequency changes of an external clock and process-voltage-temperature (PVT) variations.
In synchronous semiconductor devices, data is input and output in synchronization with an external clock. For instance, in a read operation, a synchronous semiconductor device receives a read command in synchronization with an external clock and outputs corresponding read data in synchronization with the external clock.
The time required for a synchronous semiconductor device to perform a certain action in response to an external command is referred to as latency. For instance, in a read operation, latency can indicate an amount of time between receipt of a read command and production of read data. In a synchronous semiconductor device, such latency is commonly measured in clock cycles of the external clock.
A latency signal can be used to indicate the latency of particular operations, such as read operations. Accordingly, the latency signal can be used, for instance, to indicate the availability of data after a read operation is performed.
In certain conventional devices, a latency signal is generated by latching an internal read command using a control signal. Where the frequency of an external clock increases, a margin between the internal read command signal and the control signal decreases. As a result, domain skew between the control signal (a delayed clock domain signal) and the internal read command (an external clock domain signal), which can be sensitive to changes in PVT, can produce instability in the latency signal.